Dummy Insertion Method

ABSTRACT

An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.

PRIORITY DATA

This application is a divisional application of U.S. patent applicationSer. No. 16/936,676, filed Jul. 27, 2020, which claims priority to U.S.Provisional Patent Application No. 62/907,468 filed on Sep. 27, 2019,entitled “SHDMIM DUMMY INSERTION METHOD IN SOIC” (Attorney Docket No.2019-2372/24061.4049PV01), each of which is hereby incorporated hereinby reference in its entirety.

BACKGROUND

The semiconductor integrated circuitry (IC) industry has experiencedrapid growth. Technological advances in IC design and material haveproduced generations of ICs where each generation has smaller and morecomplex circuits than previous generations. During the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased.

As the semiconductor device scaling down continues, challenges infabrication may arise. Passive devices that require large surface areasmay be moved to back-end-of-line (BEOL) structures.Metal-Insulator-Metal (MIM) capacitors are among examples of suchpassive devices. A typical MIM capacitor includes multiple conductorplate layers that are insulated from one another by multiple insulatorlayers. To alleviate uneven etch loading and nonuniform mechanicalstrength due to uneven distribution of MIM capacitors, dummy MIMstructures having comparable conductor plate layers may be inserted intoisolated regions free of MIM capacitors. Presence of through vias thatlack long-range orders poses challenges for even distribution of dummyMIM structures, resulting in less-than-optimal reduction of etch loadingand reduced mechanical strength. Therefore, although existingsemiconductor fabrication methods have been generally adequate for theirintended purposes, they have not been entirely satisfactory in everyaspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a fragmentary cross-sectional view of a device accordingaspects of the present disclosure.

FIG. 2 is a flowchart of a method for inserting dummymetal-insulator-metal (MIM) structures, according to aspects of thepresent disclosure.

FIG. 3 is a simplified block diagram of an integrated circuit (IC)manufacturing system and associated IC manufacturing flow, according toaspects of the present disclosure.

FIGS. 4, 5, 6A, 6B, 7A, 7B, 8A, and 8B are fragmentary top views of adevice at various conceptual stages of the method in FIG. 3, accordingto aspects of the present disclosure.

FIGS. 9A-9D are schematic top views of example dummy MIM structure,according to aspects of the present disclosure.

FIGS. 10A-10C are schematic cross-sectional view of a dummy MIMstructure in FIG. 9A along line I-I′, according to aspects of thepresent disclosure.

FIG. 11 is a fragmentary top view of a device according to aspects ofthe present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof various embodiments. Specific examples of components and arrangementsare described below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

Still further, when a number or a range of numbers is described with“about,” “approximate,” and the like, the term is intended to encompassnumbers that are within a reasonable range including the numberdescribed, such as within +/−10% of the number described or other valuesas understood by person skilled in the art. For example, the term “about5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

Metal-Insulator-Metal (MIM) capacitors (or super-high-density MIM,SHDMIM) have been widely used in functional circuits such as mixedsignal circuits, analog circuits, Radio Frequency (RF) circuits, DynamicRandom Access Memories (DRAMs), embedded DRAMs, and logic operationcircuits. In system-on-chip (SOC) or system-on-integrated-circuit (SOIC)applications, different capacitors for different functional circuitshave to be integrated on a same chip to serve different purposes. Forexample, in mixed-signal circuits, capacitors are used as decouplingcapacitors and high-frequency noise filters. For DRAM and embedded DRAMcircuits, capacitors are used for memory storage, while for RF circuits,capacitors are used in oscillators and phase-shift networks for couplingand/or bypassing purposes. For microprocessors, capacitors are used fordecoupling. As its name suggests, an MIM capacitor includes a sandwichstructure of interleaving metal layers and insulator layers. An exampleMIM capacitor includes a bottom conductor plate layer, a middleconductor plate layer over the bottom conductor plate layer, and a topconductor plate layer over the middle conductor plate, each of which isinsulated from an adjacent conductor plate layer by an insulator layer.As MIM capacitors are fabricated at the BEOL stage to have a largersurface area, they may be embedded in a passivation structure over aredistribution structure or an interconnect structure. MIM capacitors inan IC design may not necessarily have a uniform distribution in thepassivation structure. Due to differences in materials, construction,and thermal expansion coefficients, uneven distribution of MIMstructures in the dielectric passivation structure can lead to unevenetch loading and stress around the MIM structures and other conductivefeatures. Uneven etch loading may result in etching end-point failureand stress around the MIM structures may result in cracks anddelamination.

Dummy MIM structures may be introduced to isolated regions free of MIMstructures to provide a more even distribution of MIM structures (orsimilarly constructed dummy MIM structures) in the passivation layer.However, introduction of dummy MIM structures is not alwaysstraightforward. For example, dies in three-dimensional integratedcircuit (3DIC) or system on integrated circuit (SOIC) include throughvias that may extend through the passivation layer without beingelectrically coupled to the MIM structures. Such through vias may not beevenly distributed and present hurdles for inserting the dummy MIMstructure evenly. As a result, through vias may prevent dummy MIMstructures from being distributed evenly in isolated regions free of MIMstructures, thereby at least partially defeating the purpose of havingthe dummy MIM structures in the first place. The present disclosureprovides dummy MIM structures and methods for inserting dummy MIMstructures to provide an improved distribution of MIM structures orsimilar structures.

A fragmentary cross-sectional view of an IC device 100 is illustrated inFIG. 1. The IC device 100 may be a semiconductor device die, asemiconductor device package, or a system-on-integrated-circuit (SOIC)device. Depending on the context, the IC device 100 may represent theactual IC device or a design of the IC device 100. In embodimentsrepresented in FIG. 1, the IC device 100 includes a first die 10 that isbonded to a second die 20. Attention is first directed to the first die10. In some embodiments, the first die 10 includes a first substrate 12.The first substrate 12 includes electrical circuitry fabricated thereon.Such electrical circuitry may include passive and active microelectronicdevices, such as resistors, capacitors, inductors, diodes, p-type fieldeffect transistors (PFETs), n-type field effect transistors (NFETs),metal-oxide semiconductor field effect transistors (MOSFETs),complementary metal-oxide semiconductor (CMOS) transistors, bipolarjunction transistors (BJTs), laterally diffused MOS (LDMOS) transistors,high voltage transistors, high frequency transistors, other suitablecomponents, or combinations thereof. The first substrate 12 may alsoinclude an elementary semiconductor, a compound semiconductor, or analloy semiconductor. Examples of an elementary semiconductor includesilicon or germanium. Examples of a compound semiconductor includesilicon carbide, gallium arsenide, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide. Examples of an alloysemiconductor include silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs,GaInAs, GaInP, and/or GaInAsP, or combinations thereof. In someimplementations, the first substrate 12 is a semiconductor-on-insulatorsubstrate, such as a silicon-on-insulator (SOI) substrate, a silicongermanium-on-insulator (SGOI) substrate, or a germanium-on-insulator(GOI) substrate. As illustrated in FIG. 1, the first substrate 12extends along the X-Y plane and has a normal direction along the Zdirection. The first substrate 12 includes a first surface 12-1 and anopposing second surface 12-2. In some instances, the electricalcircuitry in the first substrate 12 may be disposed adjacent to thefirst surface 12-1. A first bottom contact pad 160 may be disposedadjacent the second surface 12-2 of the first substrate 12.

The IC device 100 also includes a first redistribution structure 14 (ora first interconnect structure 14) disposed over the first surface 12-1of the first substrate 12. The first redistribution structure 14includes various conductive components, such as metal lines, contacts,and vias, to provide horizontal and vertical electrical routing. Themetal lines are distributed in multiple metal layers, such as a firstmetal layer (e.g., a M1 layer), a second metal layer (e.g., a M2 layer),. . . and a first conductive feature 130. The first conductive feature130 is disposed on a top surface of the first redistribution structure14 away from the first substrate 12. In some embodiments, the firstconductive feature 130 may include copper, aluminum, an alloy thereof,or other conductive materials. In one embodiments, the first conductivefeature 130 may include an alloy including about 95% of aluminum andabout 5% of copper to provide adhesion with the overlying firstpassivation structure 16 (to be described below) and may be referred toas a first aluminum (Al) pad 130. Among other things, the conductivecomponents of the first redistribution structure 14 may provideelectrical connectivity to the electrical circuitry in the firstsubstrate 12. The first redistribution structure 14 also includes aplurality of dielectric layers to provide electrical isolation among thevarious conductive components, so as to prevent electrical shorting.

The first die 10 further includes a first passivation structure 16disposed on the first redistribution structure 14. The first passivationstructure 16 may include one or more silicon nitride layers, one or moresilicon carbonitride layers, one or more undoped silica glass (USG)layers, one or more silicon oxide layer deposited using high densityplasma chemical vapor deposition (HDPCVD), and one or more polymericlayers. The polymeric layers may include polyimides. A first MIMstructure 120 is embedded in the first passivation structure 16. In someexamples, the first passivation structure 16 includes a silicon nitridelayer (or a silicon carbonitride layer) disposed on the firstredistribution structure 14 and an USG layer disposed on the siliconnitride layer (or the silicon carbonitride layer). The first MIMstructure 120 is disposed on the USG layer and is blanketly covered byanother USG layer. In some instances, the first passivation structure 16also includes one or more polymeric passivation layers disposed over theUSG layer covering the first MIM structure 120. Although only the firstMIM structure 120 is shown in FIG. 1 for simplicity, the first die 10includes a plurality of MIM structures similar to the first MIMstructure 120.

The first MIM structure 120 may include two or more conductor platelayers. In one embodiment, the first MIM structure 120 includes threeconductor plate layers separated by insulator layers. In thisembodiment, the first MIM structure 120 includes a bottom conductorplate layer 1201, a middle conductor plate layer 1202 over the bottomconductor plate layer 1201, and a top conductor plate layer 1203 overthe middle conductor plate layer 1202. It is noted that the bottomconductor plate layer 1201 is formed first over a workpiece, followed bythe middle conductor plate layer 1202, and the top conductor plate layer1203. If the workpiece is thereafter flipped over, the bottom conductorplate layer 1201 may appear to be on top of the middle conductor platelayer 1202. In some implementations, each of the bottom conductor platelayer 1201, the middle conductor plate layer 1202, and the top conductorplate layer 1203 may be formed of a transition metal or a transitionmetal nitride, such as titanium (Ti), tantalum (Ta), titanium nitride(TiN), or tantalum nitride (TaN). As compared to copper or aluminum,transition metal or transition metal nitride provides better preventionof electro -migration and oxygen diffusion. Each of the bottom conductorplate layer 1201, the middle conductor plate layer 1202, and the topconductor plate layer 1203 has a thickness between about 40 nm and about80 nm. Each of the insulator layers between the bottom conductor platelayer 1201 and the middle conductor plate layer 1202 as well as betweenthe middle conductor plate layer 1202 and the top conductor plate layer1203 may be a single layer or a multi-layer formed of silicon oxide,zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, titaniumoxide, or a combination thereof. As illustrated in FIG. 1, the first die10 also includes a first top contact pad 110 disposed on a top surfaceof the first passivation structure 16 away from the first redistributionstructure 14. One or more first contact vias 140 may be extendingthrough a portion of the first MIM structure 120 between the first topcontact pad 110 and the first conductive feature 130. The one or morefirst contact vias 140 provide electrical connection to one or moreconductor plate layers in the first MIM structure 120.

The first top contact pad 110 may be formed of a metal or metal alloy,such as copper, cobalt, nickel, aluminum, tungsten, titanium, or acombination thereof. The first die 10 further includes a first throughvia 150 that extends through the first passivation structure 16, thefirst redistribution structure 14, and the first substrate 12 to beelectrically coupled to the first top contact pad 110 and the firstbottom contact pad 160. The first through via 150 may include a metalfill layer lined by a barrier layer. The metal fill layer may include ametal or a metal alloy, such as copper, cobalt, nickel, aluminum,tungsten, titanium, or a combination thereof. The barrier layer mayinclude a transition metal nitride, such as titanium nitride or tantalumnitride. Although only the first through via 150 is shown in FIG. 1 forsimplicity, the first die 10 includes a plurality of through viassimilar to the first through via 150.

The IC device 100 also includes a second die 20 bonded to the first die10 described above. For illustration purposes, the second die 20 in FIG.1 includes features similar to those in the first die 10. For example,the second die 20 includes a second substrate 22 similar to the firstsubstrate 12; a second redistribution layer 24 similar to the firstredistribution structure 14; a second passivation structure 26 similarto the first passivation structure 16; a second MIM structure 122similar to the first MIM structure 120; a second conductive feature 132similar to the first conductive feature 130; a second through via 152similar to the first through via 150; a first contact via 140 similar tothe second contact via 142; a second top contact pad 112 similar to thefirst top contact pad 110; and a second bottom contact pad 162 similarto the first bottom contact pad 160. As shown in FIG. 1, the first die10 and the second die 20 are bonded together such that the first bottomcontact pad 160 are in direct contact with the second bottom contact pad162. Detailed descriptions for similar features in the second die 20 areomitted.

Reference is still made to FIG. 1. Because the first MIM structure 120is disposed on one side of the first passivation structure 16, a firstisolated region 30 free of any MIM structure is resulted. The firstisolated region 30 is disrupted by the first through via 150 thatextends through the first passivation structure 16, clear of the firstMIM structure 120. Similarly, the disposition of the second MIMstructure 122 in the second passivation structure 26 leaves a secondisolated region 32 free of any MIM structure. In a similar fashion, thesecond isolated region 32 is disrupted by the second through via 152that extends through the second passivation structure 26. When theplacement of dummy MIM structures steers away from through vias, thedummy MIM structures may not have sufficient density to prevent etchloading and to provide satisfactory mechanical strength.

The present disclosure provides a method for inserting dummy MIMstructures in isolated regions, such as the first isolated region 30 andthe second isolated region 32. The dummy MIM structures according to thepresent disclosure include openings to accommodate through vias similarto the first through via 150 and the second through via 152.

FIG. 2 is a flowchart illustrating a method 200 for fabricating a deviceaccording to aspects of the present disclosure. Method 200 is merely anexample and is not intended to limit the present disclosure to what isexplicitly illustrated in method 200. Additional steps can be providedbefore, during, and after method 200 and some steps described herein canbe replaced, eliminated, or moved around for additional embodiments ofthe method 200. Not all steps are described herein in details forreasons of simplicity. Method 200 is described below in conjunction withFIGS. 3-5, 6A, 6B, 7A, 7B, 8A, 8B, 9A-9D, and 10.

Methods of the present disclosure, such as method 200 in FIG. 2, may beimplemented at any point between generation of an IC design layout andthe actual fabrication of the mask(s). Reference is now made to FIG. 3,which illustrates a simplified block diagram of an integrated circuit(IC) manufacturing system 300 and associated IC manufacturing flow,which may benefit from various aspects of the present disclosure. The ICmanufacturing system 300 includes a plurality of entities, such as adesign house 302, a mask house 304, and an IC manufacturer 306 (i.e., anIC fab), that interact with one another in the design, development, andmanufacturing cycles and/or services related to manufacturing anintegrated circuit (IC) device 100. The plurality of entities isconnected by a communications network, which may be a single network ora variety of different networks, such as an intranet and the Internet,and may include wired and/or wireless communication channels. Eachentity may interact with other entities and may provide services toand/or receive services from the other entities. One or more of thedesign house 302, mask house 304, and IC manufacturer 306 may have acommon owner, and may even coexist in a common facility and use commonresources.

In various embodiments, the design house 302, which may include one ormore design teams, generates an IC design layout (i.e., a design). TheIC design layout may include various geometrical patterns designed forthe fabrication of the IC device 100. By way of example, the geometricalpatterns may correspond to patterns of metal, oxide, or semiconductorlayers that make up the various components of the IC device 100 to befabricated. The various layers combine to form various features of theIC device 100. For example, various portions of the IC design layout mayinclude features such as an active region, a gate electrode, source anddrain regions, metal lines or vias of a metal interconnect, openings forbond pads, as well as other features known in the art which are to beformed within a semiconductor substrate (e.g., such as a silicon wafer)and various material layers disposed on the semiconductor substrate. Invarious examples, the design house 302 implements a design procedure toform the IC design layout. The design procedure may include logicdesign, physical design, and/or placement and routing. The IC designlayout may be presented in one or more data files having informationrelated to the geometrical patterns which are to be used for fabricationof the IC device 100. In some examples, the IC design layout may beexpressed in a GDSII file format or DFII file format.

In some embodiments, the design house 302 may transmit the IC designlayout to the mask house 304, for example, via the network connectiondescribed above. The mask house 304 may then use the IC design layout tomanufacture one or more masks to be used for fabrication of the variouslayers of the IC device 100 according to the IC design layout. Invarious examples, the mask house 304 performs mask data preparation,where the IC design layout is translated into a form that can bephysically written by a mask writer, and mask fabrication, where thedesign layout prepared by the mask data preparation is modified tocomply with a particular mask writer and/or mask manufacturer and isthen fabricated. In the example of FIG. 3, the mask data preparation andmask fabrication are illustrated as separate elements; however, in someembodiments, the mask data preparation and mask fabrication may becollectively referred to as mask preparation.

After mask data preparation and during mask fabrication, a mask or agroup of masks may be fabricated based on the modified IC design layout.For example, an electron-beam (e-beam) writer or a mechanism of multiplee-beams is used to form a pattern on a mask (photomask or reticle) basedon the modified IC design layout. The mask can be formed in varioustechnologies. In an embodiment, the mask is formed using binarytechnology. In some embodiments, a mask pattern includes opaque regionsand transparent regions. A radiation beam, such as an ultraviolet (UV)beam, used to expose a radiation-sensitive material layer (e.g.,photoresist) coated on a wafer, is blocked by the opaque region andtransmitted through the transparent regions. In one example, a binarymask includes a transparent substrate (e.g., fused quartz) and an opaquematerial (e.g., chromium) coated in the opaque regions of the mask. Insome examples, the mask is formed using a phase shift technology. In aphase shift mask (PSM), various features in the pattern formed on themask are configured to have a pre-configured phase difference to enhanceimage resolution and imaging quality. In various examples, the phaseshift mask can be an attenuated PSM or alternating PSM.

In some embodiments, the IC manufacturer 306, such as a semiconductorfoundry, uses the mask (or masks) fabricated by the mask house 304 totransfer one or more mask patterns onto a wafer and thus fabricate theIC device on the wafer. The IC manufacturer 306 may include an ICfabrication facility that may include a myriad of manufacturingfacilities for the fabrication of a variety of different IC products.For example, the IC manufacturer 306 may include a first manufacturingfacility for front end fabrication of a plurality of IC products (i.e.,front-end-of-line (FEOL) fabrication), while a second manufacturingfacility may provide back end fabrication for the interconnection andpackaging of the IC products (i.e., back-end-of-line (BEOL)fabrication), and a third manufacturing facility may provide otherservices for the foundry business (e.g., research and development). Insome embodiments, method 200 may be performed after generation of the ICdesign layout by the design house 302 but before mask fabrication at themask house 304. In some implementation, method 200 may be performedduring mask data preparation using a computer system.

Referring now to FIGS. 1 and 2, method 200 includes a block 202 where adesign (i.e., IC design layout) is received. The design may be in GDSIIof DFII format and may include features in layers constituting asemiconductor device such as the IC device 100 representatively shown inFIG. 1. In some embodiments, the design may only include features inlayers constituting a portion of the IC device 100, such as the firstdie 10, the second die 20, the first passivation structure 16, or thesecond passivation structure 26. For example, the design may include aplurality of MIM structures (similar to the first MIM structure 120 andthe second MIM structure 122) and a plurality of vias that do not gothrough the plurality of MIM structures (such as the first through via150 and the second through via 152). To be more precise, the design mayinclude information about coordinates, dimensions, and shapes of theplurality of MIM structures and the plurality of vias.

Referring to FIGS. 1, 2, 4, and 5, method 200 includes a block 204 whereisolated regions are identified based on a distribution of the pluralityof MIM structures. As described above in conjunction with FIG. 1, theplurality of MIM structures, such as the first MIM structure 120 and thesecond MIM structure 122, may not be uniformly distributed across thedevice in the design. For example, the first passivation structure 16includes the first isolated region 30 and the second passivationstructure 26 includes the second isolated region 32. By using a computersystem that is capable of reading and analyzing the design, isolatedregions in the same layer of the plurality of MIM structures may beidentified based on the distribution of the plurality of MIM structuresshown in FIG. 4. In some embodiments represented in FIG. 5, an isolatedregion template 400 may be stored in a database accessible to thecomputer system. The isolated region template 400 may be square orrectangular in shape and may have a predetermined area, which may bebetween about 0.001 times and about 1 times of an average area of theplurality of MIM structures. In some other embodiments, the isolatedregion template 400 may have a rhombus shape, a diamond shape, or astair-like shape. In some instances, the isolated region template 400may have an area between about 1 μm² and about 250000 μm². In theseembodiments, a region that is free of any MIM structures may beidentified as a part of the isolated regions when the isolated regiontemplate 400 may fit in that region. Conversely, a region that is freeof any MIM structures may nevertheless be excluded from the isolatedregions when the isolated region template 400 does not fit in thatregion.

Referring to FIGS. 2, 6A, and 6B, method 200 includes a block 206 wherea plurality of dummy MIM shapes (such as rectangular dummy MIM shapes400A or square dummy MIM shapes 400B) in the isolated regions aredetermined. For the simplicity of calculation, a plurality of dummy MIMshapes (400A/400B) may be stored in a database accessible by thecomputer system for performing the method 200. In some embodiments, eachof the dummy MIM shapes (400A/400B) may be rectangular (as shown in FIG.6A, 400A), square (as show in FIG. 6B, 400B), rhombus, or polygonal inshape or may be stair-shaped. In some implementations, the computersystem for performing the method 200 operates to select a single dummyMIM shape and fit as many of the dummy MIM shapes in the identifiedisolated regions. At block 206, the computer system ensures that each ofplurality of dummy MIM shapes (such as 400A or 400B) is spaced away fromadjacent MIM structures (such as the by a minimum spacing). The minimumspacing may be determined based on process parameters and desiredprocess margins. The minimum spacing is needed to ensure that the dummyMIM shapes are isolated from the MIM structure.

It is noted that at least in some embodiments, operations at block 204and 206 do not consider the dimensions and shapes of the plurality ofvias (such as the first through vias 150 and the second through vias 152in FIG. 1). That is, operations at blocks 204 and 206 do not regard theplurality of vias as obstructive features in placing the plurality ofdummy MIM structures. As will be described below, instead of avoidingthe plurality of vias, methods of the present disclosure utilizeopenings to accommodate the plurality of vias when any of the pluralityof vias passes through the dummy MIM structures.

Referring to FIGS. 2, 7A and 7B, method 200 includes a block 208 where asubset of the plurality of vias (such as through vias 150 or 152 shownin FIG. 1) that overlap the plurality of dummy MIM shapes 400A/400B isidentified. In some embodiments illustrated in FIGS. 7A and 7B, not allof the plurality of vias (such as through vias 150 or 152 shown inFIG. 1) overlap with the dummy MIM shapes 400A or 400B. The computersystem for performing the operations of method 200 may compare thelayers of the design that include the dummy MIM shapes 400A or 400B withthe layers of the design that include the plurality of vias in order toidentify the subset of the plurality of vias that overlap the pluralityof dummy MIM shapes.

Referring to FIGS. 2, 8A, and 8B, method 200 includes a block 210 wherea plurality of opening shapes for the subset of the plurality of viasare determined. In some embodiments shown in FIG. 8A, a first openingshape 500A that overlaps each of the plurality of rectangular dummy MIMshapes 400A is determined. That is, each of the plurality of therectangular dummy MIM shapes 400A is fitted with a first opening shape500A. Similarly, in some embodiments shown in FIG. 8B, a second openingshape 500B that overlaps each of the plurality of square dummy MIMshapes 400B is determined. Each of the plurality of square dummy MIMshapes 400B is fitted with a second opening shape 500B. Operations atblock 210 continue until all of the subset of the plurality of vias areoverlapped with the plurality of opening shapes. In some embodimentsshown in FIGS. 8A and 8B, each of the plurality of opening shapes iscircular in shape and operations at block 210 are performed such that anareal center or a weight center of each of the plurality of openingshapes is aligned with an areal center or a weight center of each of theplurality of vias. In some instances not specifically shown in FIGS. 8Aand 8B, some of the plurality of openings shapes may not land squarelyon the plurality of dummy MIM shapes. In these embodiments where each ofthe plurality of opening shapes is circular, each of the plurality ofopening shapes is greater than the via it overlaps in terms of area onthe X-Y plane. In other words, a cross-sectional area of the opening isgreater than that of the via along the Z direction, which isperpendicular to the substrate or die.

Referring to FIGS. 2 and 9A-9D, method 200 includes a block 212 wherethe plurality of opening shapes are super-positioned onto the pluralityof dummy MIM shapes to obtain a plurality of final dummy MIM structures.After the plurality of dummy MIM shapes are determined based on thedistribution of the plurality of MIM structures at block 208 andplurality of opening shapes are fitted onto the subset of plurality ofvias at block 210, the plurality of opening shapes are super-positionedonto the plurality of the dummy MIM shapes at block 212 to obtain thefinal dummy MIM structures. Examples of the such super-position areshown in FIGS. 9A-9D. Referring to FIG. 9A, a first opening shape 500Ais super-positioned onto a rectangular dummy MIM shape 400A to obtaininga final dummy MIM structure (similar to the dummy MIM structure 170 or172 in FIG. 11). Referring to FIG. 9B, a second opening shape 500B issuper-positioned onto a square dummy MIM shape 400B to obtain a finaldummy MIM structure (similar to the dummy MIM structure 170 or 172 inFIG. 11). Referring to FIG. 9C, a third opening shape 500C issuper-positioned onto a diamond or rhombus dummy MIM shape 400C to forma final dummy MIM structure (similar to the dummy MIM structure 170 or172 in FIG. 11). Referring to FIG. 9D, a fourth opening shape 500D issuper-positioned onto a stair-shaped dummy MIM shape 400D to obtain afinal dummy MIM structure (similar to the dummy MIM structure 170 or 172in FIG. 11). Each of the opening shapes in FIGS. 9A-9D represents anopening in the respective MIM structure to accommodate one of theplurality of vias.

Referring to FIG. 2, method 200 includes a block 214 where the pluralityof final dummy MIM structures are inserted into the design to obtain amodified design. At block 214, the final dummy MIM structuresrepresentatively shown in FIGS. 9A-9D are inserted into the design toobtain a modified design. Reference is made to FIG. 3. In terms of theIC manufacturing flow, the final dummy MIM structures in FIGS. 9A-9D maybe inserted into the design (i.e., IC design layout) received from thedesign house 302 to obtain a modified design.

To ensure satisfactory process windows and avoid undesirablecapacitance, each of the first opening shape 500A, second opening shape500B, third opening shape 500C, and the fourth opening shape 500D issubstantially coaxial with the first through via 150 (or the secondthrough via 152, as the case may be) and is spaced apart from the firstthrough via 150 (or the second through via 152, as the case may be) by aspacing S. In some instances, the spacing S may be between about 1 μmand about 2 μm. To ensure uniform stress distribution and to preventcrack propagation, the edges of the first opening shape 500A, secondopening shape 500B, third opening shape 500C, and the fourth openingshape 500D spaced apart from an edge of the first dummy MIM structure170 (or the second dummy MIM structure 172, as the case may be) by aminimum margin M. In some instances, the minimum margin M is betweenabout 1 μm and about 2 μm. It is observed that when the spacing S isless than 1 μm the process window may be reduced as overlay errors maycause the first through via 150 (or the second through via 152) to comein contact with the first dummy MIM structure 170 (or the second dummyMIM structure 172). When the spacing S and the minimum margin M aregreater than 2 μm, the overall dimension of the first dummy MIMstructure 170 (or the second dummy MIM structure 172) may be too large,making it less efficient to be inserted into the isolated regions.

The dummy MIM structure may have different dummy conductor platearrangements. To illustrate, example cross-sectional views of the dummyMIM structure in FIG. 9A along line I-I′ is illustrated in FIGS. 10A,10B, and 10C. As shown in FIGS. 10A, 10B and 10C, the first dummy MIMstructure 170 (or the second dummy MIM structure 172, as the case maybe) includes a bottom dummy conductor plate layer 1701, a middle dummyconductor plate layer 1702 over the bottom dummy conductor plate layer1701, and a top dummy conductor plate layer 1703 over the middle dummyconductor plate layer 1702. Out of these three dummy conductor platelayers, the bottom dummy conductor plate layer 1701 is formed first andthe middle dummy conductor plate layer 1702 and the top dummy conductorplate layer 1703 are sequentially formed over the bottom dummy conductorplate layer 1701. In some embodiments, like the conductor plate layersin the first MIM structure 120 and the second MIM structure 122, thebottom dummy conductor plate layer 1701, the middle dummy conductorplate layer 1702, and the top dummy conductor plate layer 1703 areinsulated from one another by at least one insulator layers. Dependingon the orientation of the first die 10 and the second die 20, the bottomdummy conductor plate layer 1701 may come out on top for the first dummyMIM structure 170 or may drop to the bottom for the second dummy MIMstructure 172. The different orientations are shown in FIG. 11 (to bedescribed below).

In some embodiments represented in FIG. 10A, the bottom dummy conductorplate layer 1701, the middle dummy conductor plate layer 1702, and thetop dummy conductor plate layer 1703 are coextensive and the firstopening shape 500A is duplicated in each of the dummy conductor platelayers. In some embodiments represented in FIG. 10B, the first openingshape 500A is accommodated in the bottom dummy conductor plate layer1701 but the openings in the middle dummy conductor plate layer 1702 andthe top dummy conductor plate layer 1703 are larger than the firstopening shape 500A. In some embodiments represented in FIG. 10C, thebottom dummy conductor plate layer 1701 is patterned before thedeposition of the middle dummy conductor plate layer 1702 such that themiddle dummy conductor plate layer 1702 may extend over sidewalls of thebottom dummy conductor plate layer 1701. In the embodiments shown inFIG. 10C, the first opening shape 500A is defined by the patterns in themiddle dummy conductor plate layer 1702. Similar dummy conductor platelayer arrangements may be implemented in embodiments in the dummy MIMstructure shown in FIGS. 9B, 9C or 9D.

Referring to FIGS. 2 and 11, method 200 includes a block 216 where an ICdevice 100′ is fabricated based on the modified design. In someinstances, the mask house 304 may fabricate masks based on the modifieddesign obtained at block 214 and deliver the masks to the ICmanufacturer 306. The IC manufacturer 306 may then fabricate the ICdevice 100′ shown in FIG. 11. At this point, the dummy MIM structuresinserted into the modified design are embodied in the IC device 100′. Ascompared to the IC device 100 in FIG. 1, the IC device 100′ additionallyincludes a first dummy MIM structure 170 in the first isolated region 30in FIG. 11 and a second dummy MIM structure 172 in the second isolatedregion 32 in FIG. 11. With respect to the first die 10 in FIG. 11, thefirst dummy MIM structure 170 is one of a plurality of dummy MIMstructures disposed in isolated regions in the IC device 100′. Withrespect to the first die 20 in FIG. 11, the second dummy MIM structure172 is one of a plurality of dummy MIM structures disposed in isolatedregions in the IC device 100′. The first dummy MIM structure 170includes a first opening 180 to accommodate the first through via 150.With respect to the X-Y cross-sectional plane, the first opening 180 isgreater than the first through via 150 such that the first dummy MIMstructure 170 is spaced apart from the first through via 150. Similarly,the second dummy MIM structure 172 includes a second opening 182 toaccommodate the second through via 152. With respect to the X-Ycross-sectional plane, the second opening 182 is greater than the secondthrough via 152 such that the second dummy MIM structure 172 is spacedapart from the second through via 152.

The first dummy MIM structure 170 and the second dummy MIM structure 172are shown in FIG. 11 as having dummy conductor plate layer arrangementssimilar to those shown in FIG. 10A. In other embodiments, they may havedummy conductor plate layer arrangement shown in FIGS. 10B or 10C. Forthe avoidance of doubts, the first dummy MIM structure 170 and thesecond dummy MIM structure 172 may have the shapes, structures andopenings illustrated in FIGS. 9A, 9B, 9C, or 9D. For example, the firstopening 180 and the second opening 182 may correspond to the firstopening shape 500A in FIG. 9A, the second opening shape 500B in FIG. 9B,the third opening shape 500D in FIG. 9C, or the third opening shape 500Cin FIG. 9D.

The dummy MIM structures of the present disclosure include structuressubstantially comparable to those of functional MIM structures.Reference is still made to FIG. 11. As described above, the first MIMstructure 120 includes a bottom conductor plate layer 1201, a middleconductor plate layer 1202, and a top conductor plate layer 1203. Insome implementations, each of the bottom conductor plate layer 1201, themiddle conductor plate layer 1202, and the top conductor plate layer1203 may be formed of a transition metal or a transition metal nitride,such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), ortantalum nitride (TaN). In some implementations illustrated in FIG. 11,the first dummy MIM structure 170 includes a bottom dummy conductorplate layer 1701, a middle dummy conductor plate layer 1702 over thebottom dummy conductor plate layer 1701, and a top dummy conductor platelayer 1703 over the middle dummy conductor plate layer 1702. Each of thebottom dummy conductor plate layer 1701, the middle dummy conductorplate layer 1702, and the top dummy conductor plate layer 1703 may beformed of a transition metal or a transition metal nitride, such astitanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalumnitride (TaN). The bottom conductor plate layer 1201 and the bottomdummy conductor plate layer 1701 may be formed simultaneously in thesame process steps. In similar fashion, the middle conductor plate layer1202 and the middle dummy conductor plate layer 1702 may be formedsimultaneously and the top conductor plate layer 1203 and the top dummyconductor plate layer 1703 may be formed simultaneously. In someinstances, at least a portion of the bottom conductor plate layer 1201may be coplanar with at least a portion of the bottom dummy conductorplate layer 1701; at least a portion of the middle conductor plate layer1202 may be coplanar with at least a portion of the middle dummyconductor plate layer 1702; and at least a portion of the top conductorplate layer 1203 may be coplanar with at least a portion of the topdummy conductor plate layer 1703. Like the first MIM structure 120, thebottom dummy conductor plate layer 1701, the middle dummy conductorplate layer 1702, and the top dummy conductor plate layer 1703 arerespectively insulated from one another by one or more insulator layers.The same may be said with respect to the second MIM structure 122 andthe second dummy MIM structure 172. The second MIM structure 122 and thesecond dummy MIM structure 172 may have similar compositions formed inthe same process steps. The dummy conductor plate layers in the seconddummy MIM structure 172 are also insulated from one another by one ormore insulator layers. Different from the functional first MIM structure120 and the second MIM structure 122, the first dummy MIM structure 170and the second dummy MIM structure 172 are electrically floating. Thatis, the first dummy MIM structure 170 and the second dummy MIM structure172 are not electrically coupled to any functional structures in the ICdevice 100′.

Based on the above discussions, it can be seen that the presentdisclosure offers advantages over conventional methods and devices. Itis understood, however, that other embodiments may offer additionaladvantages, and not all advantages are necessarily disclosed herein, andthat no particular advantage is required for all embodiments. Oneadvantage is that the methods of the present disclosure allow insertionof dummy MIM structures around through vias to provide an improveddistribution of MIM structure or dummy MIM structures, so as to preventuneven etch loading or cracks around the MIM structures. Anotheradvantage is that methods of the present disclosure consider presence ofthe through vias without letting the through vias to obstruct insertiondummy MIM structures.

Thus, the present disclosure provides an IC device. The IC deviceincludes a substrate including a first surface and a second surfaceopposing the first surface, a redistribution layer disposed over thefirst surface and including a conductive feature, a passivationstructure disposed over the redistribution layer, ametal-insulator-metal (MIM) capacitor embedded in the passivationstructure, a dummy MIM feature embedded in the passivation structure andincluding an opening, a top contact pad over the passivation structure,a contact via extending between the conductive feature and the topcontact pad, and a through via extending through the passivationstructure and the substrate. The dummy MIM feature is spaced away fromthe MIM capacitor and the through via extends through the opening of thedummy MIM feature without contacting the dummy MIM feature.

In some embodiments, the conductive feature includes aluminum. In someimplementations, the MIM capacitor includes a first bottom conductorplate, a first middle conductor plate over the first bottom conductorplate, and a first top conductor plate over the first middle conductorplate. In some instances, the dummy MIM feature includes a second bottomconductor plate, a second middle conductor plate over the second bottomconductor plate, and a second top conductor plate over the second middleconductor plate. In some implementations, the first bottom conductorplate and the second bottom conductor plate are coplanar. In omsinstances, the dummy MIM feature is electrically floating. In someembodiments, the opening is circular. In some implementations, the dummyMIM feature includes a square shape, a rectangular shape, or a stairshape when viewed from a direction normal to the substrate. In someembodiments, the IC device may further include a bottom contact pad overthe second surface of the substrate, wherein the through via extendsbetween and is electrically coupled to the top contact pad and thebottom contact pad.

The present disclosure also provides a method. The method includesreceiving a design that includes a plurality of metal-insulator-metal(MIM) structures and a plurality of vias that do not extend through theplurality of MIM structures, determining a plurality of dummy MIMshapes, identifying a subset of the plurality of vias that overlap theplurality of dummy MIM shapes, determining a plurality of opening shapesover the subset of the plurality of vias, super-positioning theplurality of dummy MIM shapes and the plurality of opening shapes toobtaining a plurality of final dummy MIM structures, and inserting theplurality of final dummy MIM structures in the design to obtain amodified design.

In some embodiments, each of the plurality of dummy MIM shapes includesa square shape, a rectangular shape, or a stair shape. In someimplementations, each of the plurality of opening shapes includes acircular shape. In some embodiments, the determining of the plurality ofdummy MIM shapes is based on a distribution of the plurality of MIMstructures. In some instances, each of the plurality of MIM structuresand each of the plurality of final dummy MIM structures include a bottomconductor plate, a middle conductor plate over the bottom conductorplate, and a top conductor plate over the middle conductor plate. Insome embodiments, the method may further include fabricating anintegrated circuit (IC) device based on the modified design. In someimplementations, the fabricating of the IC device includessimultaneously forming the plurality of MIM structures and the pluralityof final dummy MIM structures.

The present disclosure further provides a method. The method includesreceiving a design that includes a substrate, a redistribution layerdisposed over the substrate and including a conductive feature, apassivation structure disposed over the redistribution layer, aplurality of metal-insulator-metal (MIM) capacitors embedded in thepassivation structure, and a plurality of through via extending throughthe passivation structure and the substrate, the plurality of throughvia being spaced apart from the plurality of MIM capacitors. The methodfurther includes determining a plurality of dummy MIM shapes based on adistribution of the plurality of MIM capacitors in the passivationstructure, identifying a subset of the plurality of through vias thatoverlap the plurality of dummy MIM shapes, determining a plurality ofopening shapes over the subset of the plurality of through vias,super-positioning the plurality of dummy MIM shapes and the plurality ofopening shapes to obtaining a plurality of final dummy MIM structures,and inserting the plurality of final dummy MIM structures in the designto obtain a modified design.

In some embodiments, each of the plurality of opening shapes is greaterthan a cross sectional area of each of the subset of the plurality ofthough vias along a direction perpendicular to the substrate. In someimplementations, each of the plurality of dummy MIM shapes includes asquare shape, a rectangular shape, or a stair shape and each of theplurality of opening shapes includes a circular shape. In someinstances, the method may further include fabricating an integratedcircuit (IC) device based on the modified design.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, comprising: receiving a design thatincludes a plurality of metal-insulator-metal (MIM) structuresidentifying isolated regions among the plurality of MIM structures;fitting a plurality of dummy MIM structures into the isolated regions;after the fitting, inserting the plurality of dummy MIM structures inthe design; and after the inserting, fabricating a semiconductorstructure on a substrate based on the design.
 2. The method of claim 1,wherein the design further includes a plurality of vias that do notextend through the plurality of MIM structures.
 3. The method of claim2, further comprising: before the inserting, determining a plurality ofopenings in the plurality of dummy MIM structures that are directlyoverlapping with the plurality of vias; and incorporating the pluralityof openings into the design.
 4. The method of claim 3, wherein each ofthe plurality of openings comprises a circular shape.
 5. The method ofclaim 3, wherein each of the plurality of openings is greater than across sectional area of each of the plurality of though vias along adirection perpendicular to the substrate.
 6. The method of claim 1,wherein each of the plurality of dummy MIM structures comprises a squareshape, a rectangular shape, or a stair shape.
 7. The method of claim 1,wherein each of the plurality of MIM structures and each of theplurality of dummy MIM structures comprise a bottom conductor plate, amiddle conductor plate over the bottom conductor plate, and a topconductor plate over the middle conductor plate.
 8. The method of claim7, wherein the bottom conductor plate, the middle conductor plate andthe top conductor plate are interleaved by a plurality of insulatorlayers.
 9. The method of claim 8, wherein the bottom conductor plate,the middle conductor plate and the top conductor plate comprise titanium(Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN),wherein the plurality of insulator layers comprise silicon oxide,zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, titaniumoxide, or a combination thereof.
 10. A method, comprising: receiving adesign that includes a plurality of metal-insulator-metal (MIM)structures and a plurality of vias that do not extend through theplurality of MIM structures; determining a plurality of dummy MIMshapes; identifying a subset of the plurality of vias that overlap theplurality of dummy MIM shapes; determining a plurality of opening shapesover the subset of the plurality of vias; super-positioning theplurality of dummy MIM shapes and the plurality of opening shapes toobtaining a plurality of final dummy MIM structures; and inserting theplurality of final dummy MIM structures in the design to obtain amodified design.
 11. The method of claim 10, wherein each of theplurality of dummy MIM shapes comprises a square shape, a rectangularshape, or a stair shape.
 12. The method of claim 10, wherein each of theplurality of opening shapes comprises a circular shape.
 13. The methodof claim 10, wherein the determining of the plurality of dummy MIMshapes is based on a distribution of the plurality of MIM structures.14. The method of claim 10, wherein each of the plurality of MIMstructures and each of the plurality of final dummy MIM structurescomprise a bottom conductor plate, a middle conductor plate over thebottom conductor plate, and a top conductor plate over the middleconductor plate.
 15. The method of claim 10, further comprisingfabricating an integrated circuit (IC) device based on the modifieddesign.
 16. The method of claim 15, wherein the fabricating of the ICdevice comprises simultaneously forming the plurality of MIM structuresand the plurality of final dummy MIM structures.
 17. A method,comprising: receiving a design that comprises: a substrate, aredistribution layer disposed over the substrate and including aconductive feature, a passivation structure disposed over theredistribution layer, a plurality of metal-insulator-metal (MIM)capacitors embedded in the passivation structure, and a plurality ofthrough via extending through the passivation structure and thesubstrate, the plurality of through via being spaced apart from theplurality of MIM capacitors; determining a plurality of dummy MIM shapesbased on a distribution of the plurality of MIM capacitors in thepassivation structure; identifying a subset of the plurality of throughvias that overlap the plurality of dummy MIM shapes; determining aplurality of opening shapes over the subset of the plurality of throughvias; super-positioning the plurality of dummy MIM shapes and theplurality of opening shapes to obtaining a plurality of final dummy MIMstructures; and inserting the plurality of final dummy MIM structures inthe design to obtain a modified design.
 18. The method of claim 17,wherein each of the plurality of opening shapes is greater than a crosssectional area of each of the subset of the plurality of though viasalong a direction perpendicular to the substrate.
 19. The method ofclaim 17, wherein each of the plurality of dummy MIM shapes comprises asquare shape, a rectangular shape, or a stair shape, wherein each of theplurality of opening shapes comprises a circular shape.
 20. The methodof claim 17, further comprising fabricating an integrated circuit (IC)device based on the modified design.